SH7764 Datasheet, PDF (343/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.4.12 Bus Control Register (BCR)
Bit: 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IRSD[2:0]
DPUP  OPUP     BREQEN   
Initial value: 0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R/W R/W R/W R/W R R/W R R R R R/W R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0






 IPUP 




 ASYNC1 ASYNC0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R/W R R R R R R R/W R/W
Initial
Bit
Bit Name Value R/W
63 to 30 
All 0 R
29 to 27 IRSD2 to 111 R/W
IRSD0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Idle Cycles between SRAM Access and SDRAM
Access
These bits specify the number of idle cycles to be
inserted between SRAM access (areas 0 and 3) and
SDRAM access (areas 1 and 2).
000: 4 idle cycles
001: 5 idle cycles
010: 6 idle cycles
011: 7 idle cycles
100: 8 idle cycles
101: 9 idle cycles
110: 10 idle cycles
111: 11 idle cycles
Rev. 1.00 Nov. 22, 2007 Page 287 of 1692
REJ09B0360-0100