SH7764 Datasheet, PDF (1336/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
Figure 25.1 shows a block diagram of the FLCTL.
DMAC
DMA transfer
requests
(2 lines)
Peripheral bus
32
Peripheral bus interface
32 32
32
32
Registers
Interrupts
(4 lines)
State
machine
QTSEL
FCKSEL
FIFO
256 bytes
ECC
Transmission/
reception
control
×1, ×1/2,
×1/4
CPG
FCLK
Peripheral clock Pck
8
8
8
FLCTL
Note: FCLK is an operating clock for interface signals with flash memory.
It is specified by the CPG.
FLASH IF
8
Control signal
NAND
FLASH
Figure 25.1 FLCTL Block Diagram
Rev. 1.00 Nov. 22, 2007 Page 1280 of 1692
REJ09B0360-0100