SH7764 Datasheet, PDF (1529/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 User Break Controller (UBC)
Data values and execution count are not included in the conditions.
With the above settings, the user break occurs after executing the instruction at address
H'00008000 to H'00008FFE where ASID is H'80 or before executing the instruction at address
H'00008010 to H'00008016 where ASID is H'70.
(2) Match Conditions are Specified for an Operand Access Cycle
• Example 2-1
Register settings: CBR0 = H'40800023 / CRR0 = H'00002001 / CAR0 = H'00123456 /
CAMR0 = H'00000000 / CBR1 = H'4070A025 / CRR1 = H'00002001 / CAR1 =
H'000ABCDE / CAMR1 = H'000000FF / CDR1 = H'0000A512 / CDMR1 = H'00000000 /
CETR1 = H'00000000 / CBCR = H'00000000
Specified conditions: Independent for channels 0 and 1
 Channel 0
Address: H'00123456 / Address mask: H'00000000 / ASID: H'80
Bus cycle: Operand bus, operand access, and read (operand size is not included in the
conditions.)
 Channel 1
Address: H'000ABCDE / Address mask: H'000000FF / ASID: H'70
Data: H'0000A512 / Data mask: H'00000000 / Execution count: H'00000000
Bus cycle: Operand bus, operand access, write, and word size
Execution count is not included in the conditions.
With these settings, the user break occurs for channel 0 for the following accesses: longword
read access to address H'000123454, word read access to address H'000123456, byte read
access to address H'000123456 where ASID is H'80. The user break occurs for channel 1
when word H'A512 is written to address H'000ABC00 to H'000ABCFE where ASID is H'70.
Rev. 1.00 Nov. 22, 2007 Page 1473 of 1692
REJ09B0360-0100