SH7764 Datasheet, PDF (307/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 10 Clock Pulse Generator (CPG)
10.4.1 Frequency Control Register (FRQCR)
FRQCR is a 32-bit read-only register used to confirm the division ratios for the CPU clock (Ick),
SHwy clock (SHck), peripheral clock (Pck), and the bus clock (Bck) after a power-on reset. For
the frequency ratios, refer to table 10.2, Clock Operating Mode. This register can be accessed only
in longwords. Operation cannot be guaranteed if this register is written to.
FRQCR is only initialized by a power-on reset caused by the PRESET pin or watchdog timer
overflow.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—————————
CFC[2:0]
—
BFC[2:0]
Initial value: — — — — 0
0
0
0
0
0
1
1
0
0
1
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
—————————
Initial value: 0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R
6
5
4
PFC[2:0]
1
0
0
RRR
3
2
1
0
—— — —
0
1
0
0
RRRR
Bit
Bit Name Initial Value R/W
31 to 28 —
Undefined R
27 to 23 —
All 0
R
22 to 20 CFC[2:0] 011
R
19
—
0
R
18 to 16 BFC[2:0] 010
R
15 to 7 —
All 0
R
Description
Reserved
These bits are read as B'0011 when the clock
operating mode is mode 2, and read as B'0100
when mode 3.
Reserved
These bits are always read as all 0.
CPU Clock (Ick) and SHwy Clock (SHck)
Frequency Division Ratios
CFC[2:0] Ick SHck
011:
×1 ×1/3
Reserved
This bit is always read as 0.
Bus Clock (Bck) Frequency Division Ratio
010: ×1/3
Reserved
These bits are always read as all 0.
Rev. 1.00 Nov. 22, 2007 Page 251 of 1692
REJ09B0360-0100