SH7764 Datasheet, PDF (266/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 8 Caches
• Data array
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on.
• LRU
In a 4-way set-associative method, up to 4 items of data can be registered in the cache at each
entry address. When an entry is registered, the LRU bit indicates which of the 4 ways it is to be
registered in. The LRU mechanism uses 6 bits of each entry, and its usage is controlled by
hardware. The LRU (least-recently-used) algorithm is used for way selection, and selects the
less recently accessed way. The LRU bits are initialized to 0 by a power-on reset. The LRU
bits cannot be read from or written to by software.
Rev. 1.00 Nov. 22, 2007 Page 210 of 1692
REJ09B0360-0100