SH7764 Datasheet, PDF (1070/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
22.3.4 LCDC Start Address Register for Upper Display Data Fetch (LDSARU)
LDSARU sets the start address from which data is fetched by the LCDC for display of the LCDC
panel. When a DSTN panel is used, this register specifies the fetch start address for the upper side
of the panel.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16




SAU[27:16]
Initial value: 0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SAU[15:4]




Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
Bit
Bit Name Initial Value R/W
31 to 28 
All 0
R
27
SAU[27] 0
R/W
26
SAU[26] 1
R/W
25 to 4 SAU[25:4] All 0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Start Address for Upper Display Data Fetch
The start address for data fetch of the display data
must be set within the SDRAM area of area 1 or 2.
3 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: The minimum alignment unit of LDSARU is 512 bytes. Write 0 to the lower nine bits.
Rev. 1.00 Nov. 22, 2007 Page 1014 of 1692
REJ09B0360-0100