SH7764 Datasheet, PDF (694/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDMCNT[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WDMCNT[15:4]




Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
Bit
31 to 4
3 to 0
Initial
Bit Name Value R/W
WDMCNT All 0 R/W
[31:4]

All 0 R
Description
WDMA Transfer Count
These bits set the data transfer count during WDMA
transfer. The following transfer count should be
selected according to the WDMA maximum burst size.
1 burst: 8 × n [H'08 × n] (bytes)
2 bursts: 16 × n [H'10 × n] (bytes)
4 bursts: 32 × n [H'20 × n] (bytes)
Reserved
These bits are always read as 0. The write value should
always be 0.
18.3.6 DMA Control Registers 0 to 5 (SSIDMCOR0 to SSIDMCOR5)
SSIDMCOR0 to SSIDMCOR5 is a 32-bit readable/writable register that controls the operations
and stop for SSI_DMAC0/1 and selects serial bit clocks other than the port function. This register
value is initialized when either of the conditions is implemented such as hardware reset, software
reset or software reset for SSI_DMAC (DMRST bit in SSIDMACOR0 to SSIDMACOR3).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DM TX RX
RST RST RST













Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0



SCKSOP[2:0]
SCKSIP[2:0]
SCKS[2:0]

RPT
MD
TRMD DMEN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 638 of 1692
REJ09B0360-0100