SH7764 Datasheet, PDF (456/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
12.4.5 Repeat Mode Transfer
In a repeat mode transfer, a DMA transfer is repeated without specifying the transfer settings
every time before executing a transfer.
Using a repeat mode transfer with the half end function allows a double buffer transfer executed
virtually. Following processings can be executed effectively by using a repeat mode transfer. As
an example, operation of receiving data from the external memory and handling it is explained.
In the following example, handling 40-word data every data reception is explained.
1. DMAC settings
• Set address of the external memory in SAR
• Set address of an internal memory data store area in DAR
• Set TCR to H'50 (80 times)
• Satisfy the following settings of CHCR
Bits RPT[2:0] = B'010: Repeat mode (use DAR as a repeat area)
Bit HIE = B'1: TCR/2 interrupt generated
Bits DM[1:0] = B'01: DAR incremented
Bits SM[1:0] = B'00: SAR fixed
Bit IE = B'1: Interrupt enabled
Bit DE = B'1: DMA transfer enabled
• Set such as bits TB and TS[2:0] according to use conditions
• Set bits CMS[1:0] and PR[1:0] in DMAOR according to use conditions and set the DME bit to
B'1
2. DMA transfer is executed.
3. TCR is decreased to half of its initial value and an interrupt is generated
After reading CHCR to confirm that the HE bit is set to 1 by an interrupt processing, clear the HE
bit to 0 and handle 40-word data from the address set in DAR.
4. TCR is cleared to 0 and an interrupt is generated
After reading CHCR to confirm that the TE bit is set to 1 by an interrupt processing, clear the
TE bit to 0 and handle 40-word data from the address set in DAR + 40. After this operation,
the value of DARB is copied to DAR in DMAC and initialized, and the value of TCRB is
copied to TCR and initialized to 80.
5. Hereafter, steps 2 and 4 are repeated until the DME or DE bit is cleared to 0, or an NMI
interrupt is generated.
Rev. 1.00 Nov. 22, 2007 Page 400 of 1692
REJ09B0360-0100