SH7764 Datasheet, PDF (480/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.5 Interrupt Mask Register (INTMSK)
INTMSK is 32-bit readable and writable with conditions registers that control mask settings for
each IRQn (n = 0, 1) interrupt request. To clear the mask settings for interrupts, write 1 to the
corresponding bits in INTMSKCLR. Writing 0 to bits in INTMSK is invalid.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM00 IM01              
Initial value: 1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value R/W Description
31
IM00
1
R/W Sets masking of an
[When reading]
independent interrupt
0: Interrupts are accepted
request of IRQ0.
1: Interrupts are masked
30
IM01
1
R/W Sets masking of an
independent interrupt
[When writing]
request of IRQ1.
0: Invalid
1: Interrupts are masked
29 to 0 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 424 of 1692
REJ09B0360-0100