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SH7764 Datasheet, PDF (117/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series | |||
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Section 3 Instruction Set
Instruction
Operation
Instruction Code
Privileged T Bit New
MOVT
Rn
T â Rn
0000nnnn00101001 â
ââ
SWAP.B Rm,Rn
Rm â swap lower 2 bytes 0110nnnnmmmm1000 â
â Rn
ââ
SWAP.W Rm,Rn
Rm â swap upper/lower
words â Rn
0110nnnnmmmm1001 â
ââ
XTRCT
Rm,Rn
Rm:Rn middle 32 bits â Rn 0010nnnnmmmm1101 â
ââ
Note: * The assembler of Renesas uses the value after scaling (Ã1, Ã2, or Ã4) as the
displacement (disp).
Table 3.5 Arithmetic Operation Instructions
Instruction
Operation
ADD
Rm,Rn Rn + Rm â Rn
ADD
#imm,Rn Rn + imm â Rn
ADDC
Rm,Rn
Rn + Rm + T â Rn,
carry â T
ADDV
Rm,Rn
Rn + Rm â Rn,
overflow â T
CMP/EQ #imm,R0 When R0 = imm, 1 â T
Otherwise, 0 â T
CMP/EQ Rm,Rn
When Rn = Rm, 1 â T
Otherwise, 0 â T
CMP/HS Rm,Rn
When Rn ⥠Rm (unsigned),
1âT
Otherwise, 0 â T
CMP/GE Rm,Rn
When Rn ⥠Rm (signed),
1âT
Otherwise, 0 â T
CMP/HI
Rm,Rn
When Rn > Rm (unsigned),
1âT
Otherwise, 0 â T
CMP/GT Rm,Rn
When Rn > Rm (signed),
1âT
Otherwise, 0 â T
CMP/PZ Rn
When Rn ⥠0, 1 â T
Otherwise, 0 â T
CMP/PL Rn
When Rn > 0, 1 â T
Otherwise, 0 â T
Instruction Code
Privileged T Bit
0011nnnnmmmm1100 â
â
0111nnnniiiiiiii â
â
0011nnnnmmmm1110 â
Carry
New
â
â
â
0011nnnnmmmm1111 â
Overflow â
10001000iiiiiiii â
0011nnnnmmmm0000 â
0011nnnnmmmm0010 â
Comparison â
result
Comparison â
result
Comparison â
result
0011nnnnmmmm0011 â
Comparison â
result
0011nnnnmmmm0110 â
Comparison â
result
0011nnnnmmmm0111 â
Comparison â
result
0100nnnn00010001 â
0100nnnn00010101 â
Comparison â
result
Comparison â
result
Rev. 1.00 Nov. 22, 2007 Page 61 of 1692
REJ09B0360-0100
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