SH7764 Datasheet, PDF (426/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
12.3.7 DMA Channel Control Registers (CHCR0 to CHCR5)
CHCR are 32-bit readable/writable registers that control the DMA transfer mode.
Bit:
Initial value:
R/W:
31 30 29
LCKN
0
1
0
R R/W R
28 27 26 25 24 23 22 21 20 19 18 17 16
RPT[2:0]
DO
DVMD TS[2] HE HIE AM AL
0
0
0
0
0
0
00
0
0
0
0
0
R R/W R/W R/W R R/W R R/W R/W R/(W)* R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DM[1:0]
SM[1:0]
RS[3:0]
DL DS TB TS[1:0] IE TE DE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W
Note: Writing 0 is possible to clear the flag.
Bit
31
30
29, 28
Bit Name
—
Initial
Value
0
LCKN
1
—
All 0
R/W
R
R/W
R
Descriptions
Reserved
This bit is always read as 0. The write value should
always be 0.
Bus Lock Signal Disable
Specifies whether enable or disable the bus lock signal
output when a load instruction is output in dual transfer
mode. This bit is effective in cycle steal mode.
To disable the bus lock signal, the bus request from the
bus master other than the DMAC could be received,
and so improve the bus usage efficiency in total system.
Further, the initial value must be cleared to 0 in burst
mode. And in the case of specifying the USB in an on-
chip module request mode, the bit should be set to 1.
0: Bus lock signal output enabled
1: Bus lock signal output disabled
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 370 of 1692
REJ09B0360-0100