SH7764 Datasheet, PDF (807/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.2 Register Descriptions
Table 20.1 shows the configuration of registers of the E-DMAC. Table 20.2 shows the state of
registers in each processing mode.
Table 20.1 Register Configuration
Name
Abbreviation R/W
E-DMAC mode register
EDMR
R/W
E-DMAC transmit request register EDTRR
R/W
E-DMAC receive request register
EDRRR
R/W
Transmit descriptor list start address TDLAR
R/W
register
Receive descriptor list start address RDLAR
R/W
register
EtherC/E-DMAC status register
EESR
R/W
EtherC/E-DMAC status interrupt
EESIPR
R/W
permission register
Transmit/receive status copy enable TRSCER
R/W
register
Receive missed-frame counter
RMFCR
R
register
Transmit FIFO threshold register
TFTR
R/W
FIFO depth register
FDR
R/W
Receiving method control register RMCR
R/W
Transmit FIFO Underrun Counter
TFUCR
R/W
Receive FIFO Overflow Counter
RFOCR
R/W
Receive buffer write address register RBWAR
R
Receive descriptor fetch address
RDFAR
R
register
Transmit buffer read address register TBRAR
R
Transmit descriptor fetch address
TDFAR
R
register
Flow Control Start FIFO Threshold FCFTR
R/W
Setting Register
Receive Data Padding Insert Register RPADIR
R/W
P4 Area
Address*
H'FEF0 0000
H'FEF0 0008
H'FEF0 0010
H'FEF0 0018
H'FEF0 0020
H'FEF0 0028
H'FEF0 0030
H'FEF0 0038
H'FEF0 0040
H'FEF0 0048
H'FEF0 0050
H'FEF0 0058
H'FEF0 0064
H'FEF0 0068
H'FEF0 00C8
H'FEF0 00CC
H'FEF0 00D4
H'FEF0 00D8
H'FEF0 0070
H'FEF0 0078
Area 7
Address*
H'1EF0 0000
H'1EF0 0008
H'1EF0 0010
H'1EF0 0018
H'1EF0 0020
H'1EF0 0028
H'1EF0 0030
H'1EF0 0038
H'1EF0 0040
H'1EF0 0048
H'1EF0 0050
H'1EF0 0058
H'1EF0 0064
H'1EF0 0068
H'1EF0 00C8
H'1EF0 00CC
H'1EF0 00D4
H'1EF0 00D8
H'1EF0 0070
H'1EF0 0078
Access
Size
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Rev. 1.00 Nov. 22, 2007 Page 751 of 1692
REJ09B0360-0100