SH7764 Datasheet, PDF (1247/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
Bit 31—Software Reset (SRES): Resets the G2D.
Bit 31: SRES Description
0
Command processing execution is enabled.
1
This bit is set to 1 when a hardware reset is performed.
(Initial value)
Clear this bit to 0 in initialization.
When this bit is set to 1 by software, a reset is performed for drawing operations
only. The G2D registers are also initialized.
While this bit is set to 1, this is the only register that can be written to.
Note: For the software reset to be correctly reflected in this LSI, a method for
reflecting and confirming write access is necessary, similar to that for
memory access. Accordingly, after a software reset starts, execute the
following processing before the software reset is canceled.
1. When the G2D priority is equal to the CPU priority, execute dummy read
three times for a random SDRAM area.
2. When the G2D priority is level 2 whereas the CPU priority is level 3,
execute dummy read once for a random SDRAM area.
3. When the G2D priority is level 3 whereas the CPU priority is level 2,
finish all SDRAM accesses by modules of level 2 or level 3, excluding
the G2D.
Bits 30 to 1—Reserved: The write value should always be 0. These bits are always read as 0.
Bit 0—Rendering Start (RS): Specifies the start of rendering. During the drawing period (from
rendering start to TRAP command execution), writing 1 to this bit is prohibited.
Bit 0: RS
0
1
Description
Rendering is not started. (Initial value)
Rendering is started. This bit is cleared to 0 after rendering starts.
(2) Status Register (SR)
Offset:
H'004
Initial Value: H'80000000
The status register (SR) is a 32-bit read-only register used to read the internal status of the G2D
from outside.
SR is initialized as follows at a hardware reset:
Rev. 1.00 Nov. 22, 2007 Page 1191 of 1692
REJ09B0360-0100