SH7764 Datasheet, PDF (435/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
Bit
9, 8
7 to 3
2
Initial
Bit Name Value
PR[1:0] 00
—
All 0
AE
0
R/W Descriptions
R/W Priority Mode 1, 0
Select the priority level between channels when there
are transfer requests for multiple channels
simultaneously.
00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5
01: CH0 > CH2 > CH3 > CH1 > CH4 > CH5
10: Setting prohibited
11: Round-robin mode
When round-robin mode is specified, do not mix the
cycle steal mode and burst mode in channels 0 to 5
respectively.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)* Address Error Flag
Indicates that an address error occurred during DMA
transfer.
This bit is set under following conditions:
• The value set in SAR or DAR does not match to the
transfer size boundary.
• The transfer source or transfer destination is invalid
space.
• The transfer source or transfer destination is in
module stop mode
If this bit is set, DMA transfers in the corresponding
channels (channels 0 to 5) are all disabled even if the
DE bit in CHCR and the DME bit in DMAOR0 are set to
1.
0: No DMAC address error
[Clearing condition]
Writing AE = 0 after AE = 1 read
1: DMAC address error occurs
Rev. 1.00 Nov. 22, 2007 Page 379 of 1692
REJ09B0360-0100