SH7764 Datasheet, PDF (60/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 1 Overview
Items
Specification
Memory management • 4-Gbyte address space, 256 address space identifiers (8-bit ASIDs)
unit (MMU)
• Single virtual memory mode and multiple virtual memory mode
• Supports multiple page sizes: 1 Kbyte, 4 Kbytes, 8 Kbytes, 64 Kbytes,
256 Kbytes, 1 Mbyte, 4 Mbytes, and 64 Mbytes
• 4-entry fully-associative TLB for instructions
• 64-entry fully-associative TLB for instructions and operands
• Supports software-controlled replacement and random-counter
replacement algorithm
• TLB contents can be accessed directly by address mapping
• Access right check
Cache memory
• Instruction cache (IC)
 32-Kbyte, 4-way set associative
 256 entries/way, 32-byte block length
 Power-down function (way prediction)
• Operand cache (OC)
 32-Kbyte, 4-way set associative
 256 entries/way, 32-byte block length
• Single-stage copy-back buffer and single-stage write-through buffer
• Store queue (32 bytes × 2 entries)
On-chip memory
• 16-Kbyte fast RAM
(IL memory)
• Consists of one page
• Accessible from the following three read/write ports
 SuperHyway bus
 Cache/RAM internal bus
 Instruction bus
• Supports 8-, 16-, 32-, or 64-bit operand access from the CPU
• Supports 8-, 16-, 32-, or 64-bit access and 16- or 32-byte access
through external requests
Rev. 1.00 Nov. 22, 2007 Page 4 of 1692
REJ09B0360-0100