SH7764 Datasheet, PDF (340/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Example:
(a) LTAD[8:0] = = B'010000000
LTAM[8:0] = = B'111111000
In the above case, the address space in which bits 28 to 23 of an address are B'010000
(8 Mbytes) is translated to tiled memory space.
(b) LTAD[8:0] = = B'001010101
LTAM[8:0] = = B'111111100
In the above case, the address space in which bits 28 to 22 of an address are B'0010101
(4 Mbytes) is translated to tiled memory space.
(c) LTAM[8:0] = = B'111111111
In the above case, an address space of 1 Mbyte is translated to tiled memory space.
(d) LTAM[8:0] = = B'110000000
In the above case, an address space of 128 Mbytes (whole space) is translated to tiled memory
space.
Note that, this register should be set while the SDRAM is not accessed by any modules; for
example, during initial setting after a power on (except for auto-refreshing).
11.4.11 Request Mask Setting Register (RQM)
Bit: 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
       NMIME        LCDM
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R/W R R R R R R R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
     VDCM    2DDM 2DCM   ATAM  
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R R R R/W R/W R R R/W R R
Rev. 1.00 Nov. 22, 2007 Page 284 of 1692
REJ09B0360-0100