SH7764 Datasheet, PDF (378/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.6.3 Read-Strobe Negate Timing
When the SRAM interface is used, the negation timing of the strobe signal during a read operation
can be specified through the RDH bit in CSnWCR.
CLKOUT
T_AS1 T₁ T_S1 T_W T_W T_W T_W T₂ T_H1 T_H2 T_AH1
A25 to A0
CSn
R/W
RD
(read)
D31 to D0
(read)
TS1: RD setup wait
CSnWCR RDS
(0 to 7)
TAS1: Address setup wait
CSnWCR ADS
(0 to 7)
TW: Access wait
CSnWCR IW
(0 to 25)
*¹
TH1,TH2: RD hold wait
CSnWCR RDH
(0 to 7)
TAH1: Address hold wait
CSnWCR AHS
(0 to 7)
WE
(write)
CLKOUT
CLKOUT
D31 to D0
(ADS = 0)
(write)
D31 to D0
(ADS = 1 to 7)
(write)
BS
TS1: WE setup wait
CSnWCR WTS
(0 to 7)
TAS1: Address setup wait
CSnWCR ADS
(0 to 7)
TW: Access wait
CSnWCR IW
(0 to 25)
*²
TH1,TH2: WE hold wait
CSnWCR WTH
(0 to 7)
TAH1: Address hold wait
CSnWCR ADH
(0 to 7)
Notes: 1. When CSnBCR RDSPL is set to 1.
2. When CSnWCR.BSH is set to 1.
Figure 11.9 SRAM Interface Wait State Timing (Read-Strobe Negate Timing Setting)
Rev. 1.00 Nov. 22, 2007 Page 322 of 1692
REJ09B0360-0100