SH7764 Datasheet, PDF (811/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.2.3 E-DMAC Receive Request Register (EDRRR)
EDRRR is a 32-bit readable/writable register that issues receive directives to the E-DMAC. After
writing 1 to the RR bit in this register, the E-DMAC reads the receive descriptor. If the RACT bit
of this receive descriptor is set to 1 (valid), the E-DMAC starts receive DMA transfer. When
DMA transfer based on the first receive descriptor is completed, the E-DMAC reads the next
receive descriptor. If the RACT bit of that receive descriptor is set to 1 (valid), the E-DMAC
continues receive DMA operation. If the RACT bit of the receive descriptor is cleared to 0
(invalid), the E-DMAC clears the RR bit and stops receive DMAC operation.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— RR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Initial
Bit
Bit Name Value R/W Description
31 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
RR
0
R/W Receive Request
0: Receiving function is disabled*
1: Receive descriptor is read, and the E-DMAC is ready
to receive
Note: * If the receiving function is disabled during frame reception, write-back is not performed
successfully to the receive descriptor. Following pointers to read a receive descriptor
become abnormal and the E-DMAC cannot operate successfully. In this case, to make
E-DMAC reception enabled again, execute a software reset by the SWR bit in EDMR.
To disable the E-DMAC receiving function without executing a software reset, specify
the RE bit in ECMR. Next, after the E-DMAC has completed the reception and write-
back to the receive descriptor has been confirmed, disable the receiving function using
this register.
Rev. 1.00 Nov. 22, 2007 Page 755 of 1692
REJ09B0360-0100