SH7764 Datasheet, PDF (1704/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Electrical Characteristics
33.4.15 FLCTL Module Signal Timing
Table 33.33 NAND Flush Memory Interface Timing
Conditions: 3.3-V power supply= 3.0 to 3.6 V, 1.2-V power supply= 1.15 to 1.35,
Ta = –20 to 85°C, –40 to 85°C
Item
Command output setup time
Command output hold time
Data output setup time
Data output hold time
Command address transmission
time 1
Command address transmission
time2
FEW cycle time
FEW low pulse width
Symbol
t
NCDS
t
NCDH
t
NDOS
t
NDOH
t_NCDAD1
t
NCDAD2
t
NWC
t
NWP
Min.
Max.
2 × t_fcyc –10 
1.5 × t_fcyc –5 
0.5
×
t
fcyc
–5

0.5
×
t
fcyc
–10

1.5
×
t
fcyc
–10

2 × t_fcyc –10 
t –5
fcyc

0.5
×
t
fcyc
–5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
FEW high pulse width
Address ready/busy transmission
time
t_NWH
t_NADRB
0.5
×
t
fcyc
–5
ns

32 × t_pcyc ns
Ready/busy data read
transmission time 1
t
NRBDR1
1.5 × t_fcyc

ns
Ready/busy data read
transmission time 2
t_NRBDR2
32
×
t
pcyc

ns
FRE cycle time
FRE low pulse width
FRE high pulse width
Read data setup time
Read data hold time
Data write setup time time
Command status read
transmission time
t_NSCC
t_fcyc –5

ns
t_NSP
0.5 × t_fcyc –5 
ns
t
NSPH
0.5 × t_fcyc –5 
ns
t
14
NRDS

ns
t
0
NRDH

ns
t
NDWS
32
×
t
pcyc

ns
t_NCDSR
4
×
t
fcyc

ns
Command output off status read t_NCDFSR
3.5 × t_fcyc

ns
transmission time
Status read setup time
t
NSTS
2.5 × t_fcyc

ns
Note: t indicates one cycle time of the FLCTL clock.
cyc
Figure
33.76, 33.80
33.76, 33.77,
33.79, 33.80
33.76, 33.77
33.77
33.77, 33.79
33.76, 33.77,
33.79, 33.80
33.77, 33.79
33.77, 33.78
33.78
33.78, 33.80
33.78
33.78, 33.80
33.79
33.80
Rev. 1.00 Nov. 22, 2007 Page 1648 of 1692
REJ09B0360-0100