SH7764 Datasheet, PDF (758/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.2 Input/Output Pins
Table 19.1 lists the pin configuration of the EtherC.
Table 19.1 Pin Configuration
Name
Abbreviation I/O Function
Transmit clock* TX-CLK
I
TX-EN, MII_TXD3 to MII_TXD0, TX-ER timing
reference signal
Receive clock*
RX-CLK
I
RX-DV, MII_RXD3 to MII_RXD0, RX-ER timing
reference signal
Transmit enable* TX-EN
O
Indicates that transmit data is ready on MII_TXD3 to
MII_TXD0
Transmit data*
MII_TXD3 to O
MII_TXD0
4-bit transmit data
Transmit error*
TX-ER
O
Notifies PHY_LSI of error during transmission
Receive data valid* RX-DV
I
Indicates that valid receive data is on MII_RXD3 to
MII_RXD0
Receive data*
MII_RXD3 to I
MII_RXD0
4-bit receive data
Receive error*
RX-ER
I
Identifies error state occurred during data reception
Carrier detection* CRS
I
Carrier detection signal
Collision detection* COL
I
Collision detection signal
Management data MDC
clock*
O
Reference clock signal for information transfer via
MDIO
Management data MDIO
I/O*
I/O Bidirectional signal for exchange of management
information between this LSI and PHY
Link status
LNKSTA
I
Inputs link status from PHY
General-purpose EXOUT
external output
O
External output pin
Wake-On-LAN
WOL
O
Signal indicating reception of Magic Packet
Notes: * MII signal conforming to IEEE802.3u
Rev. 1.00 Nov. 22, 2007 Page 702 of 1692
REJ09B0360-0100