SH7764 Datasheet, PDF (845/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
27
TFE
0
R/W Transmit Frame Error
When set to 1, this bit indicates that an error is
indicated by any of the TFS bits. (By so setting
TRSCER, it is possible to prevent this bit from being
set by an event indicated by TFS7 to TFS0. It is
impossible, however, if an event indicated by TFS7 to
TFS0 also causes TFS8 to be set.)
1: Frame transmission has been aborted.
26
TWBI
0
R/W Write-Back Completion Interrupt Notification
(This bit is valid when TRIMD is set so.)
0: nop
1: An interrupt is generated upon completion of write-
back to this descriptor.
25 to 0 TFS
All 0
R/W Transmit Frame Status
TFS25 toTFS9 [Reserved (The write value should
always be 0.)]:
TFS8 [Detect Transmit Abort];
When set to 1, this bit indicates that the abort
signal is set to 1 during frame transmission.
(causing TFE to be set)
TFS7 to TFS4 [Reserved (The write value should
always be 0.)];
TFS3 [Detect of No Carrier (corresponding to the
CND bit in EESR)];
TFS2 [Detect Loss of Carrier (corresponding to the
DLC bit in EESR)];
TFS1 [Detect of Delayed Collision during
Transmission (corresponding to the CD bit in EESR)];
TFS0 [Transmit Retry Over (corresponding to the
TRO bit in EESR)]:
When set to 1, these bits indicate that TFS8 to
TFS1 have been set to 1 during frame
transmission. (Although TFE is normally set when
these bits are set to 1, it can be prevented from
being set by so setting TRSCER.)
Rev. 1.00 Nov. 22, 2007 Page 789 of 1692
REJ09B0360-0100