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SH7764 Datasheet, PDF (241/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series | |||
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Section 7 Memory Management Unit (MMU)
The operation of the LDTLB instruction is shown in figure 7.16 and 7.17.
MMUCR
31
26 25 24 23
18 17 16 15
10 9 8 7
3210
LRUI
â
URB
â
URC
SV
â
TI â AT
Entry specification
SQMD
PTEH
31
10 9 8 7
0
VPN
â
ASID
PTEL
31 2928
10 9 8 7 6 5 4 3 2 1 0
â
PPN
â V SZ1 PR[1:0] SZ0 C D SH WT
Write
Entry 0
Entry 1
Entry 2
ASID [7:0] VPN [31:10] V
ASID [7:0] VPN [31:10] V
ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT
Entry 63 ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT
UTLB
Figure 7.16 Operation of LDTLB Instruction (TLB Compatible Mode)
Rev. 1.00 Nov. 22, 2007 Page 185 of 1692
REJ09B0360-0100
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