SH7764 Datasheet, PDF (1361/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
Bit
Bit Name
23 to 16 ECFO
[23:16]
Initial
Value R/W
H'00 R/W
15 to 8 ECFO[15:8] H'00 R/W
7 to 0 ECFO[7:0] H'00 R/W
Description
Second Data
Specify 2nd data to be input or output via the FD7 to
FD0 pins.
In write: Specify write data
In read: Store read data
Third Data
Specify 3rd data to be input or output via the FD7 to
FD0 pins.
In write: Specify write data
In read: Store read data
Fourth Data
Specify 4th data to be input or output via the FD7 to
FD0 pins.
In write: Specify write data
In read: Store read data
25.3.13 Transfer Control Register (FLTRCR)
Setting the TRSTRT bit to 1 initiates access to flash memory. Access completion can be checked
by the TREND bit. During the transfer (from when the TRSTRT bit is set to 1 until the TREND
bit is set to 1), the processing should not be forcibly ended (by setting the TRSTRT bit to 0).
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
TR TR
END STRT
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W
Bit
7 to 2
Initial
Bit Name Value
—
All 0
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 1305 of 1692
REJ09B0360-0100