SH7764 Datasheet, PDF (840/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.2.21 Transmit Interrupt Setting Register (TRIMD)
TRIMD is a 32-bit readable/writable register that specifies whether to notify write-back
completion of each frame during transmission by means of the TWB bit in EESR or the interrupt
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
— TIM —
—
— TIS
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R R R R/W
Bit
31 to 5
Bit Name

Initial
Value
All 0
4
TIM
0
3 to 1 
All 0
0
TIS
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Transmit Interrupt Mode
0: Per-transmit-frame mode
An interrupt is notified upon write-back completion of
each frame.
1: Interrupt mode
An interrupt is notified upon write-back completion of
the transmit descriptor with the TWBI bit set to 1.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Transmit Interrupt Setting
0: An interrupt is not notified in the mode selected by
the TIM bit.
When this bit is 0, the TIM bit setting is invalid.
1: An interrupt is notified by setting the TWB bit in
EESR to 1 in the mode selected by the TIM bit.
Rev. 1.00 Nov. 22, 2007 Page 784 of 1692
REJ09B0360-0100