SH7764 Datasheet, PDF (769/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
Initial
Bit
Bit Name Value R/W Description
1
MMD
0
R/W MII Management Mode
Specifies the data read/write direction with respect to
the MII.
0: Read direction is specified
1: Write direction is specified
0
MDC
0
R/W MII Management Data Clock
Outputs the value set in this bit from the MDC pin and
supplies the MII with the management data clock. For
the method of accessing the MII registers, see section
19.4.4, Accessing MII Registers.
19.3.5 MAC Address High Register (MAHR)
MAHR is a 32-bit readable/writable register that specifies the upper 32 bits of the 48-bit MAC
address. The settings in this register are normally made in the initialization process after a reset.
The MAC address setting must not be changed while the transmitting and receiving functions are
enabled. Return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR
before making settings again.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[47:32]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MA[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 0 MA[47:16] All 0
R/W MAC Address Bits 47 to 16
These bits are used to set the upper 32 bits of the MAC
address.
If the MAC address is 01-23-45-67-89-AB
(hexadecimal), set H'01234567 in this register.
Rev. 1.00 Nov. 22, 2007 Page 713 of 1692
REJ09B0360-0100