SH7764 Datasheet, PDF (13/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

9.3.1 Instruction Fetch Access from the CPU................................................................ 241
9.3.2 Operand Access from the CPU and Access from the FPU ................................... 241
9.3.3 Access from the SuperHyway Bus Master Module .............................................. 241
9.4 On-Chip Memory Protective Functions ............................................................................. 242
9.5 Usage Notes ....................................................................................................................... 243
9.5.1 Page Conflict ........................................................................................................ 243
9.5.2 Access Across Different Pages ............................................................................. 243
9.5.3 On-Chip Memory Coherency ............................................................................... 243
9.5.4 Sleep Mode ........................................................................................................... 243
Section 10 Clock Pulse Generator (CPG)..........................................................245
10.1 Features.............................................................................................................................. 245
10.2 Input/Output Pins ............................................................................................................... 248
10.3 Clock Operating Mode....................................................................................................... 249
10.4 Register Descriptions ......................................................................................................... 250
10.4.1 Frequency Control Register (FRQCR) ................................................................. 251
10.4.2 PLL Control Register (PLLCR)............................................................................ 253
10.4.3 VDC2 Clock Control Register (VDC2CLKCR)................................................... 254
Section 11 Memory Controller Unit (MCU) .....................................................255
11.1 Features.............................................................................................................................. 255
11.2 Input/Output Pins ............................................................................................................... 258
11.3 Area Overview ................................................................................................................... 260
11.3.1 Space Divisions..................................................................................................... 260
11.3.2 Memory Bus Width .............................................................................................. 261
11.3.3 Endian Setting....................................................................................................... 262
11.4 Register Description........................................................................................................... 263
11.4.1 Version Control Register (VCR)........................................................................... 266
11.4.2 Memory Interface Mode Register (MIM) ............................................................. 267
11.4.3 SDRAM Control Register (SCR).......................................................................... 271
11.4.4 SDRAM Timing Register (STR) .......................................................................... 273
11.4.5 SDRAM Row Attribute Register (SDRA)............................................................ 276
11.4.6 SDRAM Mode Register (SDMR)......................................................................... 278
11.4.7 Arbitration Mode Register (AMR) ....................................................................... 279
11.4.8 Linear-to-Tiled Memory Address Translation Control Register (LTCn).............. 280
11.4.9 Linear-to-Tiled Memory Address Translation Area Start Address Register
(LTADn) ............................................................................................................... 282
11.4.10 Linear-to-Tiled Memory Address Translation Area Start Address Mask
Register (LTAMn) ................................................................................................ 283
11.4.11 Request Mask Setting Register (RQM) ................................................................ 284
Rev. 1.00 Nov. 22, 2007 Page xiii of lvi