SH7764 Datasheet, PDF (725/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
9
PDTA
0
R/W • DWL[2:0] = 010, 011, 100, 101 (data word length:
18, 20, 22 and 24 bits), PDTA = 1 (right aligned)
The data bits which are used in SSITDR0 to
SSITDR5 or SSIRDR0 to SSIRDR5 are as follows:
Bits (number of bits having data word length
specified by DWL - 1) to 0.
If DWL[2:0] = 011, then data word length is 20 bits
and bits 19 to 0 in SSITDR0 to SSITDR5 or
SSIRDR0 to SSIRDR5 are used. All other bits are
ignored or reserved.
• DWL[2:0]= 110 (data word length: 32 bits), PDTA
ignored
All data bits in SSITDR0 to SSITDR5 or SSIRDR0 to
SSIRDR5 are used on the audio serial bus
8
DEL
0
R/W Serial Data Delay
0: 1 clock cycle delay between SSIWS[5:0] and
SSIDATA[5:0]
1: No delay between SSIWS[5:0] and SSIDATA[5:0]
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 669 of 1692
REJ09B0360-0100