SH7764 Datasheet, PDF (907/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
21.3.15 SOF Control Register (SOFCFG)
SOFCFG is a register that specifies the transaction-enabled time and BRDY interrupt status clear
timing.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
— BRDYM —
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0* 0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R R/W R
R
R
R
R
R
Initial
Bit
Bit Name
Value R/W Description
15 to 7 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
6
BRDYM
0
R/W BRDY Interrupt Status Clear Timing for each Pipe
Specifies the timing for clearing the BRDY interrupt
status for each pipe.
0: Software clears the status.
1: This module clears the status when data has been
read from the FIFO buffer or data has been
written to the FIFO buffer.
5

0*
R
Reserved
This bit is reserved. The previously read value
should be written to this bit.
Note: Although this bit is initialized to 0 by a power-
on reset, be sure to set this bit to 1 using the
initialization routine of this module.
4 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: * Although this bit is initialized to 0 by a power-on reset, be sure to set this bit to 1 using
the initialization routine of this module.
Rev. 1.00 Nov. 22, 2007 Page 851 of 1692
REJ09B0360-0100