SH7764 Datasheet, PDF (1345/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W
19, 18 ADRCNT 00
R/W
[1:0]
17
DOCMD2 0
R/W
16
DOCMD1 0
R/W
15 to 0 SCTCNT H'0000 R/W
[15:0]
Description
Address Issue Byte Count Specification
Specify the number of bytes for the address data to be
issued in address stage.
00: Issue 1-byte address
01: Issue 2-byte address
10: Issue 3-byte address
11: Issue 4-byte address
Second Command Stage Execution Specification
Specifies whether or not the second command stage is
executed in command access mode.
0: Does not execute the second command stage
1: Executes the second command stage
First Command Stage Execution Specification
Specifies whether or not the first command stage is
executed in command access mode.
0: Does not execute the first command stage
1: Executes the first command stage
Sector Transfer Count Specification [15:0]
Specify the number of sectors to be read continuously
in sector access mode. These bits are counted down for
each sector transfer end and stop when they reach 0.
These bits are used together with SCTCNT[19:16].
In command access mode, these bits are H'0 0001.
Rev. 1.00 Nov. 22, 2007 Page 1289 of 1692
REJ09B0360-0100