SH7764 Datasheet, PDF (817/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Bit
Bit Name
18
FR
17
RDE
16
RFOF
15 to 12 
11
CND
10
DLC
Initial
Value
0
0
0
All 0
0
0
R/W Description
R/W Frame Reception
Indicates that a frame has been received and the
receive descriptor has been updated. This bit is set to 1
each time a frame is received.
0: Frame has not been received
1: Frame has been received
R/W Receive Descriptor Empty
When receive descriptor empty (RDE = 1) occurs,
reception can be resumed by setting the RACT bit
(cleared to 0) of the receive descriptor to 1 and then
restarting the receive operation.
0: Receive descriptor active bit RACT = 1 detected
1: Receive descriptor active bit RACT = 0 detected
R/W Receive FIFO Overflow
Indicates that the receive FIFO has overflowed during
frame reception.
0: Overflow has not occurred
1: Overflow has occurred
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Carrier Not Detect
Indicates the carrier detection status during preamble
transmission.
0: A carrier is detected when transmission starts
1: A carrier is not detected
R/W Detect Loss of Carrier
Indicates that loss of the carrier has been detected
during frame transmission.
0: Loss of carrier has not been detected
1: Loss of carrier has been detected
Rev. 1.00 Nov. 22, 2007 Page 761 of 1692
REJ09B0360-0100