SH7764 Datasheet, PDF (1285/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Panel clock
Internal Hsync
SPL
CLS
COM
Section 24 Video Display Controller (VDC2)
Display area
Blanking interval
COM signal: When com_mode = 0: Toggles in every line (inverted in every frame)
When com_mode = 1: Inverted in every line
SPS signal: The above figure shows the waveform when VSYNC_TIM = 1 (inverted output) in SYNCNT.
Figure 24.4 Format 2 (SPS, SPL, CLS, and COM Output)
Rev. 1.00 Nov. 22, 2007 Page 1229 of 1692
REJ09B0360-0100