SH7764 Datasheet, PDF (583/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 15 Serial Communication Interface with FIFO (SCIF)
15.4 Operation
15.4.1 Overview
For serial communication, the SCIF has an asynchronous mode in which characters are
synchronized individually, and a clock synchronous mode in which communication is
synchronized with clock pulses.
The SCIF has a 16-stage FIFO buffer for both transmission and receptions, reducing the overhead
of the CPU, and enabling continuous high-speed communication. Furthermore, each channel has
RTS and CTS signals to be used as modem control signals.
The transmission format is selected in the serial mode register (SCSMR), as shown in table 15.10.
The SCIF clock source is selected by the combination of the CKE1 and CKE0 bits in the serial
control register (SCSCR), as shown in table 15.11.
(1) Asynchronous Mode
• Data length is selectable: 7 or 8 bits
• Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding
selections constitutes the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full,
overrun errors, receive data ready, and breaks.
• The number of stored data bytes is indicated for both the transmit and receive FIFO registers.
• An internal or external clock can be selected as the SCIF clock source.
 When an internal clock is selected, the SCIF operates using the clock of on-chip baud rate
generator.
 When an external clock is selected, the external clock input must have a frequency 16 or 8
times the bit rate. (The on-chip baud rate generator is not used.)
Rev. 1.00 Nov. 22, 2007 Page 527 of 1692
REJ09B0360-0100