SH7764 Datasheet, PDF (709/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLNCNTSR[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BLNCNTSR[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Initial
Bit Name Value
BLNCNTSR All 0
[31:0]
R/W Description
R/W n-Times Block Transfer Interrupt Generation Timing
These bits set the transfer block count as n-times block
transfer interrupt generation timing and SSIBLNCNT0 to
SSIBLNCNT5 increment timing.
18.3.12 n-Times Block Counters 0 to 5 (SSIBLNCNT0 to SSIBLNCNT5)
SSIBLNCNT0 to SSIBLNCNT5 is a 32-bit readable/writable register that indicates the value
incremented for each block count specified by SSIBLNCNTSR0 to SSIBLNCNTSR5 other than
the port function. This register value is initialized when either of the conditions is implemented
such as hardware reset, software reset or software reset for SSI_DMAC (DMRST bit in
SSIDMACOR0 to SSIDMACOR3).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLNCNT[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BLNCNT[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
31 to 0
Bit Name
BLNCNT
[31:0]
Initial
Value
All 0
R/W Description
R
n-Times Transfer Block Count
These bits indicate the value incremented for each
block count specified by SSIBLNCNTSR0 to
SSIBLNCNTSR5.
Rev. 1.00 Nov. 22, 2007 Page 653 of 1692
REJ09B0360-0100