SH7764 Datasheet, PDF (759/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.3 Register Descriptions
Table 19.2 shows the configuration of registers of EtherC. Table 19.3 shows the state of registers
in each processing mode.
Table 19.2 Register Configuration
Name
Abbreviation R/W
EtherC mode register
ECMR
R/W
EtherC status register
ECSR
R/W
EtherC interrupt permission register
ECSIPR
R/W
Receive frame length register
RFLR
R/W
PHY interface register
PIR
R/W
MAC address high register
MAHR
R/W
MAC address low register
MALR
R/W
PHY status register
PSR
R
Transmit retry over counter register
TROCR
R/W
Delayed collision detect counter register CDCR
R/W
Lost carrier counter register
LCCR
R/W
Carrier not detect counter register
CNDCR
R/W
CRC error frame receive counter register CEFCR
R/W
Frame receive error counter register
FRECR
R/W
Too-short frame receive counter register TSFRCR
R/W
Too-long frame receive counter register TLFRCR
R/W
Residual-bit frame receive counter
RFCR
R/W
register
Multicast address frame receive counter MAFCR
R/W
register
IPG register
IPGR
R/W
Automatic PAUSE frame register
APR
R/W
Manual PAUSE frame register
MPR
R/W
Automatic PAUSE frame retransmit count TPAUSER
R/W
register
Area 7
P4 Address* Address*
Access
Size
H'FEF0 0100 H'1EF0 0100 32
H'FEF0 0110 H'1EF0 0110 32
H'FEF0 0118 H'1EF0 0118 32
H'FEF0 0108 H'1EF0 0108 32
H'FEF0 0120 H'1EF0 0120 32
H'FEF0 01C0 H'1EF0 01C0 32
H'FEF0 01C8 H'1EF0 01C8 32
H'FEF0 0128 H'1EF0 0128 32
H'FEF0 01D0 H'1EF0 01D0 32
H'FEF0 01D4 H'1EF0 01D4 32
H'FEF0 01D8 H'1EF0 01D8 32
H'FEF0 01DC H'1EF0 01DC 32
H'FEF0 01E4 H'1EF0 01E4 32
H'FEF0 01E8 H'1EF0 01E8 32
H'FEF0 01EC H'1EF0 01EC 32
H'FEF0 01F0 H'1EF0 01F0 32
H'FEF0 01F4 H'1EF0 01F4 32
H'FEF0 01F8 H'1EF0 01F8 32
H'FEF0 0150 H'1EF0 0150 32
H'FEF0 0154 H'1EF0 0154 32
H'FEF0 0158 H'1EF0 0158 32
H'FEF0 0164 H'1EF0 0164 32
Rev. 1.00 Nov. 22, 2007 Page 703 of 1692
REJ09B0360-0100