SH7764 Datasheet, PDF (1347/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
25.3.4 Address Register (FLADR)
FLADR is a 32-bit readable/writable register that specifies an address to be output in command
access mode. In sector access mode, a physical sector number specified in the physical sector
address bits is converted into an address to be output.
• Command Access Mode
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADR[31:24]
ADR[23:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ADR[15:8]
ADR[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 24 ADR[31:24] H'00 R/W
23 to 16 ADR[23:16] H'00 R/W
15 to 8 ADR[15:8] H'00 R/W
7 to 0 ADR[7:0] H'00 R/W
Description
Fourth Address Data
Specify 4th data to be output to flash memory as an
address in command access mode.
Third Address Data
Specify 3rd data to be output to flash memory as an
address in command access mode.
Second Address Data
Specify 2nd data to be output to flash memory as an
address in command access mode.
First Address Data
Specify 1st data to be output to flash memory as an
address in command access mode.
Rev. 1.00 Nov. 22, 2007 Page 1291 of 1692
REJ09B0360-0100