SH7764 Datasheet, PDF (663/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.3.13 ATAPI Control 2 (ATAPI_CONTROL2)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WORD
SWAP
IFEN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W
Bit
31 to 2
1
Bit Name
Initial
Value
—
All 0
WORDSWAP 0
R/W Description
R
Reserved
R/W WORDSWAP controls the swapping of the upper 16-
bit data and the lower 16-bit data when the 32-bit
data bus is enabled in the pixel bus.
0: Word swap is not executed. 32-bit Data on the
pixel bus appears in a big endian format.
1: Word swap is executed between the ATAPI
interface and register/pixel bus interface. 32-bit
data on the pixel bus appears in a little endian
format.
0
IFEN
Note that word swap is only available on Data
transfer when ATAPI Control Register[0]=1: DMA
mode start. Other than DMA, all register accesses
use longword access.
0
R/W IFEN controls an ATAPI interface enable.
0: ATAPI interface disable
1: ATAPI interface enable
Note: At the value of 0, ATAPI interface I/O pins
function as input, and output pins goes high
impedance.
Rev. 1.00 Nov. 22, 2007 Page 607 of 1692
REJ09B0360-0100