SH7764 Datasheet, PDF (837/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.2.19 Flow Control Start FIFO Threshold Setting Register (FCFTR)
FCFTR is a 32-bit readable/writable register that sets the flow control of the EtherC (sets the
threshold of automatic PAUSE output). The threshold can be set in terms of the data size in the
receive FIFO (RFDO[2:0]) and the number of receive frames (RFFO[2:0]). Flow control is turned
on when either of the data size in the receive FIFO or the number of receive frames is determined
as the threshold value.
If the same receive FIFO size as set by the FIFO depth register (FDR) is set when flow control is
to be turned on according to the RFDO setting condition, flow control is turned on with (FIFO
data size − 64) bytes. For instance, when the RFD bits in FDR = 1 and the RFDO bits in this
register = 1, flow control is turned on when (2,048 − 64) bytes of data is stored in the receive
FIFO. The value set in the RFDO bits in this register should be equal to or less than the value set
in the RFD bits in FDR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
RFFO[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
R/W: R R R R R R R R R R R R R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
RFDO[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
R/W: R R R R R R R R R R R R R R/W R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 781 of 1692
REJ09B0360-0100