SH7764 Datasheet, PDF (1065/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
22.3.2 LCDC Module Type Register (LDMTR)
LDMTR sets the control signals output from this LCDC and the polarity of the data signals,
according to the polarity of the signals for the LCD module connected to the LCDC.
Bit: 15 14 13 12 11 10 9
8
7
FLM
POL
CL1
POL
DISP
POL
DPOL

MCNT CL1CNT CL2CNT 
Initial value: 0
0
0
0
0
0
0
1
0
R/W: R/W R/W R/W R/W R R/W R/W R/W R
6
5
4
3
2
1
0

MIFTYP[5:0]
0
0
0
1
0
0
1
R R/W R/W R/W R/W R/W R/W
Bit
Bit Name Initial Value R/W Description
15
FLMPOL 0
R/W FLM (Vertical Sync Signal) Polarity Select
Selects the polarity of the LCD_FLM (vertical sync
signal, first line marker) for the LCD module.
0: LCD_FLM pulse is high active
1: LCD_FLM pulse is low active
14
CL1POL 0
R/W CL1 (Horizontal Sync Signal) Polarity Select
Selects the polarity of the LCD_CL1 (horizontal sync
signal) for the LCD module.
0: LCD_CL1 pulse is high active
1: LCD_CL1 pulse is low active
13
DISPPOL 0
R/W DISP (Display Enable) Polarity Select
Selects the polarity of the LCD_M_DISP (display
enable) for the LCD module.
0: LCD_M_DISP is high active
1: LCD_M_DISP is low active
Rev. 1.00 Nov. 22, 2007 Page 1009 of 1692
REJ09B0360-0100