SH7764 Datasheet, PDF (1307/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.10 Chroma-Key Control Registers (GROPCRKY0_2 to GROPCRKY0_4)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16













 CKEN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
R/W: R/W
CROMAKR[4:0]
0
0
0
R/W R/W R/W
0
R/W
0
R/W
CROMAKG[5:0]
0
0
0
0
R/W R/W R/W R/W
0
R/W
0
R/W
CROMARKB[4:0]
0
0
0
R/W R/W R/W
0
R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 17 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
16
CKEN
0
R/W Enables or disables chroma-key processing.
0: Disables chroma-key processing
1: Enables chroma-key processing
15 to 11 CROMAKR 00000
R/W
These bits specify chroma-key target color R.
[4:0]
10 to 5 CROMAKG 000000 R/W
[5:0]
These bits specify chroma-key target color G.
4 to 0 CROMAKB 00000
R/W
These bits specify chroma-key target color B.
[4:0]
Note: Layer 1 is the bottom image which has no α control target, so the above settings are
prohibited for layer 1.
When WE =1 in GROPEDPA, the register setting is loaded in the internal circuits in
synchronization with Vsync.
While the chroma-key processing is enabled, if the graphics data values (RGB16 format) of a
pixel all match the CROMAKR[4:0], CROMAKG[5:0], and CROMAKB[4:0] settings, the pixel
color is replaced with the color (RGB16 format) specified in the chroma-key color register
(GROPCRKY1) and α processing specified through the ALPHA[7:0] bits is applied.
Chroma-keying thus enables characters or a cursor to be displayed on lower-layer graphics.
Rev. 1.00 Nov. 22, 2007 Page 1251 of 1692
REJ09B0360-0100