SH7764 Datasheet, PDF (641/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
(4) Wait for Outputting Address
1. Wait for master event (an interrupt of the MAT and MDR bits in the master status register).
2. Set the master control register to H'88 (To suspend stop the data transmission, the master
device will hold the SCL low until the MDR bit is cleared.)
3. Reset the MAT bit.
(5) Monitor of Data
1. Wait for master event, the MDR bit in the master status register.
Read data from the received data register.
If the next byte of data is the second to last byte but one to be transmitted by the slave device,
the following applies to a receive interrupt (that is, MDR interrupt) in the second to last byte
2. Set the master control register to H'8A
(set the force stop control bit).
3. Reset the MDR bit.
(6) Wait for End of Reception
1. Handle the receive interrupt (MDR) in the last byte: that is, read the data and clear the MDR.
2. Wait for the master event MST in the master status register.
3. Reset the MST bit.
Rev. 1.00 Nov. 22, 2007 Page 585 of 1692
REJ09B0360-0100