SH7764 Datasheet, PDF (752/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
(b) Reception using Interrupt Data Flow Control
Start
Release reset,
specify configuration bits
in SSICR
Enable SSI module,
enable data interrupt,
enable error interrupt
Specify TRMD, EN, SCKD,
SWSD, MUEN, DEL, PDTA,
SDTA, SPDP, SWSP, SCKP,
SWL, DWL, CHNL
EN = 1,
DIEN = 1,
UIEN = 1, OIEN = 1
Wait for interrupt
from SSI
SSI
Yes
Error interrupt?
No
Read data from
receive data register
Use SSI status register bits
to realign data
after underflow/overflow
Yes
More data to be
received?
No
Disable SSI module,
disable data interrupt
disable error IRQ,
enable idle IRQ
EN = 0,
DIEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Wait for idle interrupt
from SSI module
Reset SSI module if required
End
Figure 18.22 Reception Using Interrupt Data Flow Control
Rev. 1.00 Nov. 22, 2007 Page 696 of 1692
REJ09B0360-0100