SH7764 Datasheet, PDF (1718/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Appendix
C. Speculative Execution for Subroutine Return
The SH-4A has the mechanism to issue an instruction fetch speculatively when returning from
subroutine. By issuing an instruction fetch speculatively, the execution cycles to return from
subroutine may be shortened.
This function is enabled by setting 0 to the bit 5 (RABD) of CPU Operation Mode register
(CPUOPM). But this speculative instruction fetch may issue the access to the address that should
not be accessed from the program. Therefore, a bus access to an unexpected area or an internal
instruction address error may cause a problem. As for the effect of this bus access to unexpected
memory area, refer to appendix B, Instruction Prefetching and Its Side Effects.
Usage Condition:
When the speculative execution for subroutine return is enabled, the RTS
instruction should be used to return to the address set in PR by the JSR, BSR,
or BSRF instructions. It can prevent the access to unexpected address and
avoid the problem.
Rev. 1.00 Nov. 22, 2007 Page 1662 of 1692
REJ09B0360-0100