SH7764 Datasheet, PDF (819/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name Value R/W Description
1
PRE
0
R/W PHY-LSI Receive Error
0: PHY-LSI receive error has not been detected
1: PHY-LSI receive error has been detected
0
CERF
0
R/W CRC Error on Received Frame
0: CRC error has not been detected
1: CRC error has been detected
20.2.7 E-MAC/E-DMAC Status Interrupt Permission Register (EESIPR)
EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual
bits in the E-MAC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the
corresponding bit.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
TWB
IP
—
—
—
TABT RABT RFCOF ADE
IP
IP
IP
IP
ECI
IP
TC
IP
TDE TFUF FR RDE RFOF
IP
IP
IP
IP
IP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
CND DLC CD TRO RMAF
—
—
—
—
IP
IP
IP
IP
IP
—
Initial value: 0
0
0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W R/W R
5
4
3
2
1
0
RRF RTLF RTSF PRE CERF
—
IP
IP
IP
IP
IP
0
0
0
0
0
0
R R/W R/W R/W R/W R/W
Bit
Bit Name
31

30
TWBIP
29 to 27 
Initial
Value
0
0
All 0
R/W Description
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Write-Back Complete Interrupt Enable
0: Write-back complete interrupt is disabled
1: Write-back complete interrupt is enabled
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 763 of 1692
REJ09B0360-0100