SH7764 Datasheet, PDF (358/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Initial
Bit
Bit Name Value R/W
30 to 28 IWW2 to 111
R/W
IWW0
27

0
R
Description
Idle Cycles between Write and Read/Write and Write
Access Cycles
These bits specify the number of idle cycles to be
inserted after a write access to the memory connected
to the SRAM area (areas 0 and 3).
The idle cycles specified in these bits are inserted
between write and read cycles or between write and
write cycles, and at the same time, inserted between
accesses to area 3 and area 0 or between accesses to
area 3 and area 3.
000: No idle cycles inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 302 of 1692
REJ09B0360-0100