SH7764 Datasheet, PDF (336/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
Initial
Bit
Bit Name Value R/W
15 to 8 
All 0 R
7 to 0 PAM7 to H'00 R/W
PAM0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Pixel Bus Module Level 2 Arbitration Enable
These bits set the priority of the Pixel bus module to
level 2. The following is the correspondence between
bits and modules.
PAM[7]: G2D (command)
PAM[6]: G2D (data)
PAM[5]: (reserved)
PAM[4]: (reserved)
PAM[3]: (reserved)
PAM[2]: ATAPI
PAM[1]: (reserved)
PAM[0]: (reserved)
11.4.8 Linear-to-Tiled Memory Address Translation Control Register (LTCn)
Bit: 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTE               
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9

LTMWX[3:0]
8
7
6
5
4
3
2
1
0
        LTGBM
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R R R R R R R R R/W
Rev. 1.00 Nov. 22, 2007 Page 280 of 1692
REJ09B0360-0100