SH7764 Datasheet, PDF (229/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Memory Management Unit (MMU)
7.3.2 Instruction TLB (ITLB) Configuration
The ITLB is used to translate a virtual address to a physical address in an instruction access.
Information in the address translation table located in the UTLB is cached into the ITLB. Figure
7.8 shows the ITLB configuration. The ITLB consists of four fully-associative type entries.
Entry 0 ASID[7:0] VPN[31:10] V
Entry 1 ASID[7:0] VPN[31:10] V
Entry 2 ASID[7:0] VPN[31:10] V
Entry 3 ASID[7:0] VPN[31:10] V
PPN[28:10] SZ[1:0] SH C PR
PPN[28:10] SZ[1:0] SH C PR
PPN[28:10] SZ[1:0] SH C PR
PPN[28:10] SZ[1:0] SH C PR
Notes: 1. The D and WT bits are not supported.
2. There is only one PR bit, corresponding to the upper bit of the PR bits in the UTLB.
Figure 7.8 ITLB Configuration (TLB Compatible Mode)
7.3.3 Address Translation Method
Figure 7.9 shows a flowchart of a memory access using the UTLB.
Rev. 1.00 Nov. 22, 2007 Page 173 of 1692
REJ09B0360-0100