SH7764 Datasheet, PDF (487/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
Table 13.5 Interrupt Request Sources and INT2PRI0 to INT2PRI12
Bit
Register
28 to 24
20 to 16
12 to 8
4 to 0
INT2PRI0
TMU0 (TUNI0)
TMU0 (TUNI1)
TMU0 (TUNI2)
TMU0 (TICPI2)
INT2PRI1
TMU1 (TUNI3)
TMU1 (TUNI4)
TMU1 (TUNI5)
Reserved
INT2PRI2
SCIF0
SCIF1
WDT
Reserved
INT2PRI3
H-UDI
DMAC
Reserved
Reserved
INT2PRI4
Reserved
G2D
SSI_A (SSIDMA0) SSI_A (SSICH0)
INT2PRI5
SSI_A (SSICH1) SSI_A (SSICH2) Reserved
SSI_B
INT2PRI6
ATAPI
Reserved
FLCTL
SRC (OVF)
INT2PRI7
SCIF2
GPIO
Reserved
Reserved
INT2PRI8
Reserved
SRC (IDEI)
SRC (ODFI)
Reserved
INT2PRI9
LCDC
Reserved
Reserved
IIC
INT2PRI10 Reserved
Reserved
Reserved
Reserved
INT2PRI11 Reserved
Reserved
Reserved
Reserved
INT2PRI12 VDC2
Reserved
USB
EtherC
Note: If the value is larger, the priority is higher. Interrupt requests are masked at H'00 and H'01.
For details, see the description above.
Rev. 1.00 Nov. 22, 2007 Page 431 of 1692
REJ09B0360-0100