SH7764 Datasheet, PDF (1331/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.7 Operating Procedures
24.7.1 Display Control Block
1. Disabling register value transfer
Clear the WE bit to 0 in the SG mode register.
2. Setting the registers in the display control block
Make appropriate settings in the registers shown in table 24.9.
Specify the polarity of the external pins first.
3. Enabling register value transfer
Set the WE bit to 1 in the SG mode register.
24.7.2 Graphics Blocks
1. Disabling register value transfer
Clear the WE bit to 0 in the graphics block control registers.
Clear the WE bit to 0 in the α control registers.
2. Setting the registers in the graphics blocks
Make appropriate settings in the registers shown in tables 24.5 through 24.8.
3. Enabling register value transfer
Set the WE bit to 1 in the graphics block control registers.
Set the WE bit to 1 in the α control registers.
The display operation specified in the registers starts from the next frame.
Rev. 1.00 Nov. 22, 2007 Page 1275 of 1692
REJ09B0360-0100