SH7764 Datasheet, PDF (486/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
2. Make the MMU settings so that the address space including USERIMASK can only be
accessed by the device driver in which interrupts should be disabled.
3. Branch to the device driver.
4. Set the UIMASK bit to mask B interrupts in the device driver that is operating in user mode.
5. Process interrupts with high priority in the device driver.
6. Clear the UIMASK bit to 0 to return from processing in the device driver.
13.3.9 On-Chip Module Interrupt Priority Registers (INT2PRI0 to INT2PRI12)
INT2PRI0 to INT2PRI12 are 32-bit readable/writable registers that set priorities (levels 31 to 0) of
the on-chip peripheral module interrupts. INT2PRI0 to INT2PRI13 are initialized to H'0000 0000
by a reset.
INT2PRI0 to INT2PRI12 can set 30 priority levels (32 types of interrupt requests) to individual
interrupt sources with five bits (interrupt requests are masked at H'00 and H'01).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0


Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W
Table 13.5 shows the correspondence between interrupt request sources and bits in INT2PRI0 to
INT2PRI12.
Rev. 1.00 Nov. 22, 2007 Page 430 of 1692
REJ09B0360-0100