SH7764 Datasheet, PDF (569/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.8 Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that is used with the CKS1 and CKS0 bits in the serial mode register
(SCSMR) and the BGDM and ABCS bits in the serial extension mode register (SCEMR) to
determine the serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.
Each channel has independent baud rate generator control, so different values can be set in three
channels.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The SCBRR setting is calculated as follows:
• Asynchronous mode:
When baud rate generator operates in normal mode (when the BGDM bit of SCEMR is 0):
N=
Pch
64 × 2^2n-1 × B
×
10⁶
− 1 (Operation on a base clock with a frequency of 16 times
the bit rate)
N=
Pch
32 × 2^2n-1 × B
×
10⁶
− 1 (Operation on a base clock with a frequency of 8 times
the bit rate)
When baud rate generator operates in double speed mode (when the BGDM bit of
SCEMR is 1):
N=
Pch
× 10⁶ − 1 (Operation on a base clock with a frequency of 16 times
32 × 2^2n-1 × B
the bit rate)
N=
Pch
16 × 2^2n-1 × B
×
10⁶
− 1 (Operation on a base clock with a frequency of 8 times
the bit rate)
Rev. 1.00 Nov. 22, 2007 Page 513 of 1692
REJ09B0360-0100